Formation of Shallow p+n Junctions Using Different Annealing Schemes with Low Thermal Budget
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概要
- 論文の詳細を見る
The formation of shallow p+n junctions by directly implanting BF2 dopant into the Si substrates and then treating the samples by different annealing schemes with a low thermal budget has been studied. Nosignificant dopant diffusion is observed by using these annealing processes with a low thermal budget. After conventional furnace annealing (FA) at a medium temperature of 800°C for 30 min, the resulting junction characteristics are poor. A low-temperature long-time FA treatment at 600°C for 2 h, prior to the medium-temperature FA treatment, can considerably improve the junction formation. Furthermore, shallow p+n junctions with a leakage smaller than 10 nA/cm2 can be achieved by an annealing scheme that employs low-temperature FA followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. However, an annealing process that employs medium-temperature RTA at 800°C for 30 s followed by low-temperature FA treatment cannot produce good junctions. In addition, the low-temperature annealing time of 2–3 h is found to be sufficient for forming good shallow p+n junctions in the annealing scheme that employs low-temperature FA followed by medium-temperature RTA.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2000-03-15
著者
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Harn Sui-chan
Department Of Electronics Engineering National Taiwan University Of Science & Technology
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Juang Miin-horng
Department Of Electrical Engineering National Taiwan University Of Science And Technology
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Harn Sui-Chan
Department of Electronics Engineering, National Taiwan University of Science & Technology, Kee-Lung Rd., Taipei, Taiwan, R.O.C.
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