Single Electron Transfer Logic Gate Family
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概要
- 論文の詳細を見る
Single electron transfer logic circuits, where logical bit information is represented by the existence of discrete small current pulses accompanied by single electron tunneling (SET) in a one-dimensional array of small tunnel junctions, have been investigated. The basic operation characteristics of several key circuit elements, such as an SET transmission line, a confluence circuit, a split circuit and a set-reset gate were examined and their correct functionality was verified by Monte Carlo simulation. We have shown that basic logic gates, such as NOT, AND and OR, can be implemented using these circuit elements if we provide periodic single electron clock pulses to the gates. Robustness of these logic gates has also been investigated by calculating the dc bias margin.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1999-01-30
著者
-
Sugahara Masanori
Faculty Of Engineering Yokohama National University
-
Fukuzato Chikashi
Faculty Of Engineering Yokohama National University
-
Yoshikawa Nobuyuki
Faculty Of Agriculture Iwate University
-
Sugahara Masanori
Faculty of Engineering, Yokohama National University,
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