RC-003 Dependable Dual Edge Triggered Flip-Flops for Bloking Noise Signal

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概要

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• This paper proposes a dual edge triggered flip-flop for blocking a noise signal induced on data signal lines. The clock signal has two edges in nature, the rising edge and the falling edge. If an edge triggered flip-flop can sample data by using those two edges during one clock period, the flip-flop has the highly ability to prevent sampling the noise signal on the data line, comparing the conventional single edge triggered flip-flops. The proposed flip-flops have advantages that they do not require any additional clock/control signal and delay element to block the noise signal. Thus, their implementation/application to existing synchronous digital circuits is easy. Besides, the noise width that the proposed flip-flops can block is adjustable when the width of the clock signal is adjustable. In addition to noise signal blocking, they can apply to detection/correction of timing errors and delay faults. We show effectiveness of proposed design by circuit simulation.

• FIT(電子情報通信学会・情報処理学会)運営委員会の論文
• 2011-09-07

著者

• 三浦 幸也

  首都大

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• RC-003 Dependable Dual Edge Triggered Flip-Flops for Bloking Noise Signal

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