RC-003 Dependable Techniques for Noise Block and Delay Variation Detection/Correction
スポンサーリンク
概要
- 論文の詳細を見る
Dual edge triggered flip-flops have been proposed for noise aware design. As the clock signal has two edges in nature, rising and falling edges, if an edge triggered flipflop can sample data by using those two edges, the flipflop has the highly ability to prevent sampling a noise signal on the data line. The dual edge triggered flip-flops have advantages that they do not require any additional signal and their application to existing synchronous digital circuits is easy. This paper shows new design of the dual edge triggered flip-flops improved a circuit size and performance. In addition, a method for signal delay variation detection and correction utilized the proposed flip-flop is proposed. We show effectiveness of proposed design and application to delay variation detection/correction by circuit simulation.
- 2012-09-04
著者
関連論文
- RC-014 A Feasibility Study of Active Current Testing
- RC-011 A Case Study on Identification of Circuit Variation by Transistor States
- LC-012 Dependable Clock Design for Level Sensitive Clock Signal
- LC_007 Proposal of Dependable Clock Signal Distribution
- LC-004 Feasibility of Interconnect Open Detection by Ramp Voltage Application
- LC-005 Open Fault Detection in CMOS Combinational Circuits by Logic Testing with Precharging
- RC-003 Dependable Techniques for Noise Block and Delay Variation Detection/Correction
- RC-003 Dependable Dual Edge Triggered Flip-Flops for Bloking Noise Signal