LC-012 Dependable Clock Design for Level Sensitive Clock Signal

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概要

• 論文の詳細を見る
• FIT(電子情報通信学会・情報処理学会)推進委員会の論文
• 2007-08-22

著者

• 三浦 幸也

  首都大

関連論文

• RC-014 A Feasibility Study of Active Current Testing
• RC-011 A Case Study on Identification of Circuit Variation by Transistor States
• LC-012 Dependable Clock Design for Level Sensitive Clock Signal
• LC_007 Proposal of Dependable Clock Signal Distribution
• LC-004 Feasibility of Interconnect Open Detection by Ramp Voltage Application
• LC-005 Open Fault Detection in CMOS Combinational Circuits by Logic Testing with Precharging
• RC-003 Dependable Techniques for Noise Block and Delay Variation Detection/Correction
• RC-003 Dependable Dual Edge Triggered Flip-Flops for Bloking Noise Signal

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