RC-004 三次元ア***ロセッサ構造を用いた効率的な3D-DCT計算機構の提案(ハードウェア・アーキテクチャ,査読付き論文)

概要

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Traditional array processors randomly access to input/coefficient data stored in memory many times during the three dimensional discrete cosine transform (3D-DCT) calculation. Hence, it becomes a bottleneck of fast calculation. In this paper, a three dimensional array processor dedicated to 3D-DCT is proposed. The array processor tremendously reduces the data swapping or replacement during the calculation. Thus, it contributes to the performance improvement. The computational complexity of the proposed array processor is O(N) for an N×N×N input data cube while that of the 3D-DCT direct calculation is O(N^4). A specified I/O architecture and throughput/cost-effective architectures are also discussed for practical implementation. Experimental results of an FPGA (Field Programmable Gate Array) implementation show that our architecture has enough performance for real-time 3D-DCT calculation on its scalable architecture.
2009-08-20