Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders(Logic Synthesis and Verification,<Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper addresses parallel prefix adder synthesis which targets area minimization under given bitwise timing constraints. This problem is treated as a problem to synthesize prefix graphs which represent global structures of parallel prefix adders at technology-independent level, and a two-folded algorithm to minimize area of prefix graphs is proposed. The first process is dynamic programming based area minimization (DPAM), which focuses on a specific subset of prefix graphs and finds an exact minimum solution for the subset by dynamic programming. The subset is defined by imposing some restrictions on structures of prefix graphs. By utilizing these restrictions, DPAM can find the minimum solutions efficiently for practical bit width. The second process is area reduction with re-structuring (ARRS), which removes the imposed restrictions on structures, and restructures the result of DPAM for further area reduction while satisfying timing constraints. Experimental results show that smaller area can be achieved compared to existing methods both at prefix graph level and at gate level.
- 社団法人電子情報通信学会の論文
- 2007-12-01
著者
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Matsunaga Yusuke
Department Of Computer Science And Communication Engineering
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Matsunaga Yusuke
Department Of Computer Science And Communication Engineering Faculty Of Information Science And Elec
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MATSUNAGA Taeko
Fukuoka Laboratory for Emerging & Enabling Technology of SoC (FLEETS)
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Matsunaga Taeko
Fukuoka Laboratory For Emerging & Enabling Technology Of Soc (fleets):(present Office)graduate S
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Matsunaga Yusuke
Department Of Advanced Information Technology Faculty Of Information Science And Electrical Engineering Kyushu University
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