11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic(Integrated Electronics)
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概要
- 論文の詳細を見る
This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35μm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.
- 社団法人電子情報通信学会の論文
- 2007-03-01
著者
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Kim Jeong
Dept.of Obstetrics & Gynecology, Catholic University Medical College
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Ahn Sun
Dept. Of Electronincs Engineering Kangwon National University
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Kim Jeong
Dept. Of Arch. Eng'g Kyung Hee University
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Kim Jeong
Dept. Of Electronincs Engineering Kangwon National University
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