Level Converting Flip-Flops for High-Speed and Low-Power Applications(<Special Section>Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))

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概要

• 論文の詳細を見る

• This letter presents two high-performance level-converting flip-flops (LCFF) for multi-V_<DD> systems, indirect precharging flip-flop (IPFF) and multi-supply complementary pass-transistor flip-flop (MCPFF). Employing a simple precharging scheme, IPFF provides high operating speed. MCPFF, on the other hand, provides low power operations by implementing the edge-triggering function with complementary pass transistors. Performance comparison indicates that IPFF operates at the highest speed and MCPFF consumes the lowest power among the seven LCFFs under evaluation.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• Kim Young

  Pohang Univ. Sci. And Technol. Kor

• Kim Young

  Postech

• PARK Hyoun

  POSTECH

• Park Hyoun

  Postech Gyungbuk Kor

• LEE Bong

  POSTECH

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• Realizable Reduction of RC Networks with Current Sources for Dynamic IR-Drop Analysis of Power Networks of SoCs
• New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
• Level Converting Flip-Flops for High-Speed and Low-Power Applications(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))
• Power Modeling of Synthesizable Soft Macros(System Level Design)(VLSI Design and CAD Algorithms)
• Clock-Free MTCMOS Flip-Flops with High Speed and Low Power(Papers Selected from ITC-CSCC 2004)

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