Clock-Free MTCMOS Flip-Flops with High Speed and Low Power(<Special Section>Papers Selected from ITC-CSCC 2004)
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概要
- 論文の詳細を見る
This paper proposes two high-performance multi-threshold-voltage CMOS (MTCMOS) F/Fs that are based on the CMOS hybrid-latch F/F and the CMOS semi-dynamic F/F. The proposed F/Fs utilize a clock-gating technique or a data recovery circuit in order to preserve their logic states in the power-down mode. They can change operation modes whether the clock level is high or low, and they provide outputs to fanouts in the power-down mode. When compared with existing clock-free MTCMOS F/Fs, the proposed MTCMOS hybrid-latch F/F shows maximum reduction of average delay, average power, and average power-delay product by 33%, 46%, and 63% for the supply voltage ranging from 0.8 V to 1.2 V. Although outperformed by the MTCMOS hybrid-latch F/F, the proposed MTCMOS semi-dynamic F/F inherits the benefit of the embedded logic from the CMOS SD F/F. Experimental results indicate that the MTCMOS semi-dynamic F/F can be used to implement a logic circuit that is superior to the one designed using the MTCMOS hybrid-latch F/F in speed, power, and area.
- 社団法人電子情報通信学会の論文
- 2005-06-01
著者
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Jeong Kwang-ok
Samsung Electronics Co.
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Kim Young
Postech
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LEE Bong
POSTECH
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Lee Bong
Postech Kyungbuk Kor
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- Clock-Free MTCMOS Flip-Flops with High Speed and Low Power(Papers Selected from ITC-CSCC 2004)