Realizable Reduction of RC Networks with Current Sources for Dynamic IR-Drop Analysis of Power Networks of SoCs

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概要

• 論文の詳細を見る
• 2009-02-01

著者

• Kim Young

  Pohang Univ. Sci. And Technol. Kor

• Kim Young

  Postech

• PARK Hyoun

  POSTECH

• CHE Hong

  POSTECH

• KIM Jin

  POSTECH

関連論文

• Timing Criticality for Timing Yield Optimization
• Accelerating Relaxation Using Dynamic Error Prediction
• Realizable Reduction of RC Networks with Current Sources for Dynamic IR-Drop Analysis of Power Networks of SoCs
• New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
• Level Converting Flip-Flops for High-Speed and Low-Power Applications(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))
• Power Modeling of Synthesizable Soft Macros(System Level Design)(VLSI Design and CAD Algorithms)
• Clock-Free MTCMOS Flip-Flops with High Speed and Low Power(Papers Selected from ITC-CSCC 2004)

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