Power Modeling of Synthesizable Soft Macros(System Level Design)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We present a new approach to the power modeling ofsynthesizable soft macros, which uses the characteristics of individual input signals for high accuracy. We also present the parameterized power model, developed using the proposed approach, which can relieve us from the power characterization for all possible macro sizes. Extensive experiments illustrate that the proposed approaches exhibit the overall modeling errors below 4.24% and 4.71 % for benchmark macros before and after parameterization, when compared with the results of gate-level analysis.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• Kim Young

  Postech

• Choi Jung

  Samsung Electronics Co. Ltd.

• Do Kyung

  Postech

• KIM Yang

  POSTECH

• Choi Jung

  Samsung Electronics

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• Power Modeling of Synthesizable Soft Macros(System Level Design)(VLSI Design and CAD Algorithms)
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