Kim Young | Postech

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概要

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著作論文

Timing Criticality for Timing Yield Optimization
Accelerating Relaxation Using Dynamic Error Prediction
Realizable Reduction of RC Networks with Current Sources for Dynamic IR-Drop Analysis of Power Networks of SoCs
New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
Level Converting Flip-Flops for High-Speed and Low-Power Applications(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))
Power Modeling of Synthesizable Soft Macros(System Level Design)(VLSI Design and CAD Algorithms)
Clock-Free MTCMOS Flip-Flops with High Speed and Low Power(Papers Selected from ITC-CSCC 2004)

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