RTL design of parallel FFT with block floating point arithmetic (ワイドバンドシステム)
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概要
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In modern wireless communication systems, FFT is one of the key components but requires wide numerical dynamic range. In order to satisfy both requirements of smaller chip size and wider numerical dynamic range, we employ block floating point arithmetic rather than neither fixed point one nor floating point one to implement real systems. In this paper, we show a RTL design result in terms of a radix-4 64-point FFT with parallel architecture using block floating point arithmetic. The results show that we can get more than 100MHz clock frequency with 16-bit length or more even if we make use of FPGA devices.
- 社団法人電子情報通信学会の論文
- 2008-07-17
著者
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KUROSAKI Masayuki
Kyushu Institute of Technology
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OCHI Hiroshi
Kyushu Institute of Technology
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Ochi Hiroshi
Graduate School Of Computer Science And System Engineering Kyushu Institute Of Technology
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Setiawan Hendra
Graduate School Of Computer Science And System Engineering Kyushu Institute Of Technology
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LANANTE Leonardo
Kyushu Institute of Technology
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SETIAWAN Hendra
Kyushu Institute of Technology
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Ochi Hiroshi
Kyushu Inst. Of Technol. Fukuoka‐ken Jpn
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Kurosaki Masayuki
Graduate School Of Computer Science And System Engineering Kyushu Institute Of Technology
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- FOREWORD