DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH
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概要
- 論文の詳細を見る
A 3V 6-bit 900MSPS CMOS A/D Converter with an improved dynamic latch is proposed. It is composed of both a coarse ADC and a fine ADC whose FR(Folding Rate) is 2, NFB(Number of Folding Block) is 4, and IR(interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high-speed operation and low power consumption, further, a novel analog dynamic latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35um 2-poly 4-metal CMOS technology. The effective chip area is about 960um x 760um and it dissipates about 280mW at 3V power supply. The INL and DNL are within ±1LSB, respectively. The SNDR is about 31dB, when the input frequency reaches 40MHz at 900MHz clock frequency.
- 社団法人電子情報通信学会の論文
- 2002-06-24
著者
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Song Minkyu
Dept. Of Semiconductor Sci. Dongguk Univ.
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Oh Jinho
Dept. of Semiconductor Science, Dongguk University
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Oh Jinho
Dept. Of Semiconductor Science Dongguk University
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