AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
スポンサーリンク
概要
- 論文の詳細を見る
A 3V 8-bit 500MSPS CMOS folding/interpolation ADC is proposed. For the purpose of improving SNDR, distributed track-and-hold circuits, a novel analog latch, and digital encoder are proposed. The chip has been fabricated with a 0.35um 2-poly 3-metal CMOS technology. The effective chip area is about 1.2mm × 0.8mm and it dissipates about 210mW at 3V power supply. The INL and DNL are within ± 1LSB, respectively. The SNDR is about 43dB, when input is 50MHz.
- 社団法人電子情報通信学会の論文
- 2004-06-23
著者
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Song Minkyu
Dept. Of Semiconductor Sci. Dongguk Univ.
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Song Minkyu
Dept. Of Semiconductor Science Dongguk University
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Hwang Sanghoon
Dept. of Semiconductor Science, Dongguk University
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Hwang Sanghoon
Dept. Of Semiconductor Sci. Dongguk Univ.
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Hwang Sanghoon
Dept. Of Semiconductor Science Dongguk University
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