C-12-25 A 3V 6-b 700MSPS CMOS A/D Converter with an Improved Dynamic Latch

スポンサーリンク

概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 2001-03-07

著者

• Song Minkyu

  Dept. Of Semiconductor Sci. Dongguk Univ.

• Song Minkyu

  Dept. Of Semiconductor Science Dongguk University Seoul Korea

関連論文

• DESIGN OF A NOVEL LOGARITHMIC AMPLIFIER WITH A TWO-STEP LINEAR LIMIITING TECHNIQUE
• DESIGN OF A NOVEL LOGARITHMIC AMPLIFIER WITH A TWO-STEP LINEAR LIMIITING TECHNIQUE
• AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH
• C-12-25 A 3V 6-b 700MSPS CMOS A/D Converter with an Improved Dynamic Latch
• DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH
• A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors(Integrated Electronics)

スポンサーリンク