DESIGN OF A NOVEL LOGARITHMIC AMPLIFIER WITH A TWO-STEP LINEAR LIMIITING TECHNIQUE
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概要
- 論文の詳細を見る
In this paper, we discuss a VLSI design of a Logarithmic Amplifier(LA) for wide range and high sensitivity radar system. In general, LA consists of an input stage, a logarithmic stage, and an output stage. In order to make a much wider dynamic region and a higher speed than the conventional LA, a new mixed type of series and parallel architecture, namely a modified parallel architecture is proposed in the logarithmic stage. Further, to decrease an input range error in the front of LA, a novel input stage is designed. It is fabricated on the basis of 0.5um standard CMOS technology. Effective chip area is 1310um x 1540um, and shows the power consumption of 90mW at 3.3V supply voltage. Through the simulation and measurements, it is verified that it shows the characteristics of 60dB dynamic range and 50ns falling time.
- 社団法人電子情報通信学会の論文
- 2002-06-24
著者
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Song M
Dept. Of Semiconductor Science Dongguk University
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Song Minkyu
Dept. Of Semiconductor Sci. Dongguk Univ.
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Kim S
Dept. Of Semiconductor Science Dongguk University
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Kim Sooyeon
Dept. of Semiconductor Science, Dongguk University
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Cho Hyunryoung
RF Design Group, Gamma-Nu Inc.
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Kim Sangki
RF Design Group, Gamma-Nu Inc.
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Cho Hyunryoung
RE Design Group, Gamma-Nu Inc.
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Cho Hyunryoung
Re Design Group Gamma-nu Inc.
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Song Minkyu
RF Design Group, Gamma-Nu Inc.
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