Identification of Fixed and Interface Trap Charges in Hot-Carrier Stressed Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) through Ultraviolet Light Anneal and Gate Capacitance Measurements

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概要

• 論文の詳細を見る

• Fixed and interface trap charges in hot-carrier degraded metal oxide semiconductor field effect transistors (MOSFET's) can be distinguished by ultraviolet light (λ=253.7 nm) annealing, and observing the resultant changes in the gate-to-drain capacitance. Trapped electrons anneal readily, resulting in large changes in the gate capacitance and the threshold voltage. This suggests a trap level below the conduction band edge of SiO_2 that is smaller than the photon energy (4.9 eV). In contrast, trapped holes and interface traps do not anneal, or anneal in-significantly even after prolonged irradiation. This is consistent with a much deeper hole trap level in SiO_2, generally reported.

• 社団法人応用物理学会の論文
• 1995-01-15

著者

• Ling C

  National Univ. Singapore Singapore

• Ling C.

  Department Of Electrical Engineering National University Of Singapore

• LING C.

  Department of Electrical Enginecering, National Universiry of Singapore

関連論文

• Identification of Fixed and Interface Trap Charges in Hot-Carrier Stressed Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) through Ultraviolet Light Anneal and Gate Capacitance Measurements
• Effects of Tungsten Polycidation on the Hot-Carrier Degradation in Buried-Channel LDD p-MOSFET's
• Electron Trapping and Interface State Generation in PMOSFET's: Results from Gate Capacitance

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