Unified Gate Freezing, Gate Sizing and Buffer Insertion for Low Power CMOS Digital Circuit Design(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
スポンサーリンク
概要
- 論文の詳細を見る
One of the major factors contributing to the power dissipation in CMOS digital circuits is the switching activity. Many of such switching activities include spurious pulses, called glitches. ln this paper, we propose a new method of glitch reduction by gate freezing, gate sizing, and buffer insertion. The proposed method unifies gate freezing, gate sizing, and buffer insertion into a single optimization process to maximize the glitch reduction. The effectiveness of our method is verified experimentally using LGSynth91 benchmark circuits with a O.5^<um> standard cell library. 0ur optimization method reduces glitches by 65.64% and the power by 31.03% on average.
- 2004-06-23
著者
-
Kim J
Department Of Computer Science Sogang University
-
Kim Juho
Department Of Computer Science Sogang University
-
LEE Hyungwoo
Department of Computer Science, Sogang University
-
Shin Hakgun
Department of Computer Science, Sogang University
-
Shin Hakgun
Department Of Computer Science Sogang University
-
Lee Hyungwoo
Department Of Computer Science Sogang University
関連論文
- False-Aggressors-Aware True Crosstalk Noise Analysis with Logic Correlations for Accurate Timing Analysis(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Unified Gate Freezing, Gate Sizing and Buffer Insertion for Low Power CMOS Digital Circuit Design(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Efficient False Aggressors Pruning with Functional Correlation(Logic Synthesis)(VLSI Design and CAD Algorithms)
- Thickness Dependent Dielectric Property of BaTiO3/SrTiO3 Artificial Lattice
- Unified Gate Freezing, Gate Sizing and Buffer Insertion for Low Power CMOS Digital Circuit Design(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- False-Aggressors-Aware True Crosstalk Noise Analysis with Logic Correlations for Accurate Timing Analysis(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications(General Fundamentals and Boundaries)
- Digital Calibration Techniques for Pipelined ADCs(Analog Signal Processing)