False-Aggressors-Aware True Crosstalk Noise Analysis with Logic Correlations for Accurate Timing Analysis(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
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概要
- 論文の詳細を見る
Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix a crosstalk noise in noise analysis, it is necessary an additional design cost. Therefore, aggressor nodes that cannot affect victim node have to pruning. In this paper, we present an efficient false aggressor pruning algorithm with functional correlation. Path sensitization algorithm and logic implication approach that use functional information to identify false coupling interaction between coupled lines. 0ur experimental results show an average of 5.4% aggressor pruning and 14.6% delay reduction due to pruning.
- 社団法人電子情報通信学会の論文
- 2004-06-23
著者
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Kim Juho
Department Of Computer Science Sogang University
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LEE Hyungwoo
Department of Computer Science, Sogang University
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Lee Hyungwoo
Department Of Computer Science Sogang University
関連論文
- False-Aggressors-Aware True Crosstalk Noise Analysis with Logic Correlations for Accurate Timing Analysis(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
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- Unified Gate Freezing, Gate Sizing and Buffer Insertion for Low Power CMOS Digital Circuit Design(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- False-Aggressors-Aware True Crosstalk Noise Analysis with Logic Correlations for Accurate Timing Analysis(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))