Circuit Analysis and Design of Low-Power CMOS Tapered Buffer(Electronic Circuits)

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概要

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• Decreased power dissipation and transient voltage drops in CMOS power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits. In this paper, three CMOS buffers based on the charge-transfer, split-path and bootstrapped techniques to reduce the power dissipation and transient, voltage drop in power supply are proposed. First, the inverted-delay-unit, is used in the low-power inverted-delay-unit (LPID) CMOS buffer to eliminate the short-circuit current of the output stage. Second, the low-swing bootstrapped feedbark-controlled split-path (LBFS) CMOS buffer is proposed to eliminate the short-circuit current of the output stage by using the feedback-controlled split-path method. The dynamic power dissipation of the LBFS CMOS buffer can be reduced by limiting the gate voltage swing of the output stage. Moreover, the propagation delay of the LBFS CMOS buffer is also reduced by non-full-swing gate voltage of the output stage. Third, the charge-recovery scheme is used in the charge-transfer feedback-controlled 4-split-path (CRFS) CMOS buffer to recovery and pull up the gate voltage of the output stage for reducing power-delay product and power line noise. Based on HSPICE simulation results, the power-delay product and the transient voltage drop in power supply of the proposed three CMOS buffers can be reduced by 20% to 40% as compared to conventional CMOS tapered buffer under various capacitive load.

• 社団法人電子情報通信学会の論文
• 2003-05-01

著者

• Yang Wei-bin

  Department Of Electrical Engineering Tamkang University

• CHENG Kuo-Hsing

  Department of Electrical Engineering, Tamkang University

• Cheng Kuo-hsing

  Department Of Electrical Engineering National Central University

• Cheng Kuo-hsing

  Department Of Electrical Engineering Tamkang University

• YANG Wei-Bin

  Department of Electrical Engineering, Tamkang University

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