Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System

概要

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Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35µm CMOS process. Furthermore, these techniques are successfully verified in 14ps circuit resolution and a 500*750µm chip area for the 100-400MHz measurement range.
（社）電子情報通信学会の論文
2009-02-01