A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output

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概要

• 論文の詳細を見る

• A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13µm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146µW at 304MHz.

• （社）電子情報通信学会の論文
• 2010-03-01

著者

• Yang Wei-bin

  Department Of Electrical Engineering Tamkang University

• LO Yu-Lung

  Department of Electrical Engineering, National Kaohsiung Normal University

• CHAO Ting-Sheng

  Department of Electrical Engineering, Tamkang University

• Lo Yu-lung

  Department Of Electrical Engineering National Kaohsiung Normal University

• Lo Yu-lung

  Department Of Electrical Engineering National Central University

• Chao Ting-sheng

  Department Of Electrical Engineering Tamkang University

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