VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• This paper presents a description and an analysis of three "standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL / I). Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL / I.

• 社団法人電子情報通信学会の論文
• 1993-09-25

著者

• KOBAYASHI Hideaki

  Department of Materials Science and Processing, Faculty of Engineering, Osaka University

• KANBARA Hiroyuki

  Advanced Software Technology & Mechatronics Research Institute of Kyoto (ASTEM RI)

• Kukkal P

  Department Of Electrical And Computer Engineering University Of South Carolina

• Kukkal Pankaj

  Department Of Electrical And Computer Engineering University Of South Carolina

• Sankarshanan P.N.

  Department of Electrical and Computer Engineering, University of South Carolina

• Kanbara Hiroyuki

  Advanced Software Technology &amp Mechatronics Research Institute Of Kyoto

• Sankarshanan P.n.

  Department Of Electrical And Computer Engineering University Of South Carolina

• Kobayashi Hideaki

  Department Of Electrical And Communication Engineering Graduate School Of Engineering Tohoku Univers

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