Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment

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概要

• 論文の詳細を見る

• UDL/I test suites and UDL/I Simulation/Synthesis Environment had been developed separately in parallel. Both were designed from syntax and semantics definition of UDL/I Language Reference Manual. Through test of the UDL/I Simulation/Synthesis Environment using the UDL/I test suites, quality of the test suites and the environment had been improved. Finally all the testing result matched with expected one. It was validated that both the test suites and the environment followed UDL/I language specification.

• 社団法人電子情報通信学会の論文
• 1995-12-25

著者

• KANBARA Hiroyuki

  Advanced Software Technology & Mechatronics Research Institute of Kyoto (ASTEM RI)

• Yokota Satoshi

  Advanced Software Technology And Mechatronics Research Institute Of Kyoto (astemri)

• Kanbara Hiroyuki

  Advanced Software Technology And Mechatronics Research Institute Of Kyoto (astemri)

• Yokota Satoshi

  Advanced Software Technology and Mechatronics Research Institute of Kyoto

関連論文

• High-Level Synthesis of Software Function Calls
• Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
• VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis (Special Issue on Synthesis and Verification of Hardware Design)
• Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment

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