Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I

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概要

• 論文の詳細を見る

• This paper presents testing methods for a logic synthesis system which supports the standard HDL UDL/I, focusing on conformance test to the language specification. Conformance test, to prove that the system completely satisfies the language specification, is very important to provide a unified design environment for users of CAD tools which support the language. The basic idea of our testing methods is using a logic simulator, due to a limited schedule for the test execution. We classified the test into two : unit test and integration test. Unit test is a test of each individual functionality of the system, and integration test is a test to prove that the whole system works correctly and satisfies the, language specification. And we prepared and used various kinds of test data. One of them is the UDL/I Test Suite and it was also utilized to observe progress of language coverage by the system during the test execution.

• 社団法人電子情報通信学会の論文
• 1995-12-25

著者

• KANBARA Hiroyuki

  Advanced Software Technology & Mechatronics Research Institute of Kyoto (ASTEM RI)

• Yokota S

  Advanced Software Technology And Mechatronics Research Institute Of Kyoto

• Yokota Satoshi

  Advanced Software Technology And Mechatronics Research Institute Of Kyoto (astemri)

• Kanbara H

  Astem Ri Kyoto‐shi Jpn

• Yokota Satoshi

  Advanced Software Technology and Mechatronics Research Institute of Kyoto

関連論文

• High-Level Synthesis of Software Function Calls
• Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
• VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis (Special Issue on Synthesis and Verification of Hardware Design)
• Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment

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