A 3.3V CMOS Dual-Looped PLL with a Current-Pumping Algorithm(Special Section on Analog Circuit Techniques and Related Topics)
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概要
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This paper describes a dual-looped PLL architecture to improve voltage-to-frequency linearity of VCO.The V-I converter employing a current-pumping algorithm is proposed to enhance the linearity of the VCO circuit.The designed VCO operates at a wide frequency range of 75.8MHz-1GHz with a good linearity.The PFD circuit design technique preventing fluctuation of the charge pump circuit under the locked condition is discussed.Simulation results show that a locking time of the proposed PLL is 3.5μs at 1GHz and the power dissipation is 92mW.
- 2000-02-25
著者
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Yoon Kwang
The Department Of Electronic Engineering Inha University
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Sung Hyuk-jun
The Department Of Electronic Engineering Inha University
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