A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers(Special Section on Analog Circuit Techniques Supporting the System LSI Era)
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概要
- 論文の詳細を見る
A current-mode folding and interpolating analog to digital converter(ADC)architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 μm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity(DNL)of ±0.5LSB, an integral nonlinearity(INL)of ±1.0LSB, 20 Ms/s of the data conversion rate, and the power dissipation of 180mW with a power supply of 5 V.
- 社団法人電子情報通信学会の論文
- 2001-02-01
著者
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YOON Kwang
the Department of Electronic Engineering, Inha University
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KIM Hyung
The Department of Dermatology, Kangnam St. Mary's Hospital, College of Medicine, The Catholic Univer
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Yoon Kwang
The Dept. Of Electronic Engineering Inha University
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Yoon Kwang
The Department Of Electronic Engineering Inha University
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Kim Hyung
The Dept. Of Electronic Engineering Inha University
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Kim Hyung
The Department Of Dermatology Kangnam St. Mary's Hospital College Of Medicine The Catholic Univ
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