A 3.3V CMOS PLL with a Self-Feedback VCO (Special Section on VLSI Design and CAD Algorithms)

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概要

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• A 3.3V CMOS PLL(Phase Locked loop) with a self-feedback VCO(Voltage Controlled Oscillator) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO with a new delay cell. The proposed VCO with a self-feedback path operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC Voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 μm n-well CMOS process. The simulation results illustrate a locking time of 2.6 μsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112mW.

• 2000-12-25

著者

• YOON Kwang

  the Department of Electronic Engineering, Inha University

• Moon Yeon

  The Department Of Electronic Engineering Inha University

• Yoon Kwang

  The Department Of Electronic Engineering Inha University

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