A 3V-30 MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• A design methodology of the analog current-mode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8μm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3 mm^2. The experimental result illustrates a low power dissipation (1.0 mW-3.55 mW), 65 dB of the dynamic range, and bandwidth programmability (10 MHz-30 MHz) with an external digital 4 bit.

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• Yoon K

  Inha Univ. Inchon Kor

• YOON Kwang

  the Department of Electronic Engineering, Inha University

• HYUN Jai-Sop

  the Korea Telecommunication Research Institute

• Yoon Kwang

  The Department Of Electronic Engineering Inha University

• Hyun J‐s

  The Korea Telecommunication Research Institute

関連論文

• A 3V-30 MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator (Special Section on VLSI Design and CAD Algorithms)
• A 3.3V CMOS PLL with a Self-Feedback VCO (Special Section on VLSI Design and CAD Algorithms)
• A 3.3V CMOS Dual-Looped PLL with a Current-Pumping Algorithm(Special Section on Analog Circuit Techniques and Related Topics)
• A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers(Special Section on Analog Circuit Techniques Supporting the System LSI Era)
• An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)

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