Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
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概要
- 論文の詳細を見る
In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.
- 社団法人電子情報通信学会の論文
- 1993-03-25
著者
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Kunieda Hiroaki
The Faculty Of Engineering Tokyo Institute Of Technology
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Isshiki Tsuyoshi
The Faculty Of Engineering Tokyo Institute Of Technology
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Takeuchi Yoshinori
the Faculty of Technology, Tokyo University of Agriculture and Technology
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Takeuchi Yoshinori
The Faculty Of Technology Tokyo University Of Agriculture And Technology
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Takeuchi Yoshinori
The Faculty Of Engineering Tokyo University Of Agriculture And Technology
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