Modularization and Processor Placement for DSP Neo-Systolic Array (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
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概要
- 論文の詳細を見る
A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.
- 社団法人電子情報通信学会の論文
- 1993-03-25
著者
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Kunieda Hiroaki
The Faculty Of Engineering Tokyo Institute Of Technology
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Ito Kazuhito
The Faculty Of Engineering Tokyo Institute Of Technology
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Hagiwara Kesami
The Faculty Of Engineering Tokyo Institute Of Technology
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Shimizu Takashi
the Faculty of Engineering, Tokyo Institute of Technology
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Shimizu Takashi
The Faculty Of Engineering Tokyo Institute Of Technology
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