A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique(Integrated Electronics)
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概要
- 論文の詳細を見る
This paper presents a wide frequency range delay-locked loop implemented with a 0.35μm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10MHz to 200MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8mW and shows 13ps rms jitter at 3.3V, 150MHz condition.
- 社団法人電子情報通信学会の論文
- 2005-09-01
著者
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LEE Kang
Department of Machine Intelligence and Systems Engineering, Tohoku University
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Lee Kang‐yoon
Konkuk Univ. Seoul Kor
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Lee Kang-yoon
The Department Of Electronic Engineering Konkuk University
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Lee Kang
Department Of Electronics Engineering Konkuk University
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Lee Kang
Department Of Chemistry Research Institute Of Natural Science And Environmental Biotechnology Nation
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Lee Kang
Department of Bioengineering and Robotics, Tohoku University, 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
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