PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model : Design and Implementation of Its Prototype Processor
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概要
- 論文の詳細を見る
Reconfigurable architectures have been focused for its potential on achieving high preformance by reconfigureing special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution mode. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750 MHz.
- 社団法人電子情報通信学会の論文
- 2003-05-01
著者
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KOJIMA Akira
Faculty of Information Sciences, Hiroshima City University
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Hironaka Tetsuo
Faculty Of Computer Sciences Hiroshima City University
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Hironaka Tetsuo
Faculty Of Information Sciences Hiroshima City University
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Yoshida Noriyoshi
Faculty Of Engineering Hiroshima University
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Yoshida Noriyoshi
Faculty Of Information Sciences Hiroshima City University
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TANIGAWA Kazuya
Graduate School of Information Sciences, Hiroshima City University
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Tanigawa Kazuya
Graduate School Of Information Sciences Hiroshima City University
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Kojima Akira
Faculty Of Engineering Tokai University
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