A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
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概要
- 論文の詳細を見る
- 2012-02-01
著者
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INAGI Masato
Graduate School of Information Sciences, Hiroshima City University
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Inagi Masato
Graduate School Of Information Sciences Hiroshima City University
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Tanigawa Kazuya
Graduate School Of Information Sciences Hiroshima City University
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Hironaka Tetsuo
Graduate School Of Information Sciences Hiroshima City University
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NAKAMURA Masatoshi
Graduate School of Information Sciences, Hiroshima City University
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SATO Masayuki
Taiyo Yuden Co., Ltd
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ISHIGURO Takashi
Taiyo Yuden Co., Ltd
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Nakamura Masatoshi
Graduate School Of Information Sciences Hiroshima City University
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Ishiguro Takashi
Taiyo Yuden Co. Ltd
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Sato Masayuki
Taiyo Yuden Co. Ltd
関連論文
- A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os(Discrete Mathematics and Its Applications)
- Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
- PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model : Design and Implementation of Its Prototype Processor
- A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks