A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay [7], [8]. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.
- 社団法人電子情報通信学会の論文
- 1994-12-25
著者
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Koide T
Hiroshima Univ. Higashi‐hiroshima‐shi Jpn
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Koide Tetsushi
Faculty Of Engineering Hiroshima University
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YOSHIDA NORIYOSHI
Faculty of Engineering, Hiroshima University
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Katsura Yoshinori
Faculty of Engineering, Hiroshima University
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Yamatani Katsumi
Information Systems Div., MAZDA Motor Corporation
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Yoshida Noriyoshi
Faculty Of Information Sciences Hiroshima City University:oki Electric Co. Ltd.
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Yoshida Noriyoshi
Faculty Of Engineering Hiroshima University
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Katsura Yoshinori
Faculty Of Engineering Hiroshima University
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Yamatani Katsumi
Information Systems Div. Mazda Motor Corporation
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