Yoshida Noriyoshi | Faculty Of Engineering Hiroshima University
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概要
関連著者
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Yoshida Noriyoshi
Faculty Of Engineering Hiroshima University
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YOSHIDA NORIYOSHI
Faculty of Engineering, Hiroshima University
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Koide T
Hiroshima Univ. Higashi‐hiroshima‐shi Jpn
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Koide Tetsushi
Faculty Of Engineering Hiroshima University
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Yoshida Noriyoshi
Faculty Of Information Sciences Hiroshima City University:oki Electric Co. Ltd.
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Suzuki Takeshi
Faculty of Agriculture, Kobe University
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Kikuno Tohru
Faculty Of Engineering Hiroshima University
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KOJIMA Akira
Faculty of Information Sciences, Hiroshima City University
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Hironaka Tetsuo
Faculty Of Computer Sciences Hiroshima City University
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Hironaka Tetsuo
Faculty Of Information Sciences Hiroshima City University
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Katsura Yoshinori
Faculty of Engineering, Hiroshima University
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Yamatani Katsumi
Information Systems Div., MAZDA Motor Corporation
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Isomoto Kazunori
Technical Research Center (Hiroshima), MAZDA Motor Corporation
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Mimasa Yoshiyasu
Faculty of Engineering, Hiroshima University
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Yoshida Noriyoshi
Faculty Of Information Sciences Hiroshima City University
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TANIGAWA Kazuya
Graduate School of Information Sciences, Hiroshima City University
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Katsura Yoshinori
Faculty Of Engineering Hiroshima University
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Mimasa Yoshiyasu
Faculty Of Engineering Hiroshima University
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Tanigawa Kazuya
Graduate School Of Information Sciences Hiroshima City University
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Isomoto Kazunori
Technical Research Center (hiroshima) Mazda Motor Corporation
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Kojima Akira
Faculty Of Engineering Tokai University
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Suzuki Takeshi
Faculty Of Engineering Hiroshima University
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Yamatani Katsumi
Information Systems Div. Mazda Motor Corporation
著作論文
- On Common Sequence Problems (Applied Combinatorial Theory and Algorithms)
- Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities (Special Issue on Synthesis and Verification of Hardware Design)
- An Efficient Timing-Driven Global Routing Method for Standard Cell Layout (Special Issue on Synthesis and Verification of Hardware Design)
- A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout (Special Section on VLSI Design and CAD Algorithms)
- A Graph Bisection Algorithm Based on Subgraph Migration (Special Section on VLSI Design and CAD Algorithms)
- PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model : Design and Implementation of Its Prototype Processor