CMOS Implementation of a Multiple-Valued Memory Cell Using Λ-Shaped Negative-Resistance Devices(<Special Section>Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
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概要
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In this paper, we propose the CMOS implementation of a multiple-valued memory cell using Λ-shaped negative-resistance devices. We first propose the construction of a multiple-stable circuit that consists of Λ-shaped negative-resistance devices from four enhancement-mode MOS-FETs without a floating voltage source, and connect this in parallel with a unit circuit. It is shown that the movement of Λ-shaped negative-resistance characteristics in the direction of the voltage axis is due to voltage sources.Furthermore, we propose the construction of a multiple-valued memory cell using a multiple-stable circuit. It is shown that it is possible to write and hold data. If the power supply is switched on, it has a feature which enables operation without any electric charge leakage. It is possible, by connecting Λ-shaped negative-resistance devices in parallel, to easily increase the number of multiple values.
- 社団法人電子情報通信学会の論文
- 2004-04-01
著者
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Sekine Yoshifumi
Department Of Electronics & Computer Science College Of Science & Technology Nihon Universit
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Sekine Yoshifumi
Department Of Electronic Engineering College Of Science And Technology Nihon University
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Saeki K
Department Of Electronics & Computer Science College Of Science & Technology Nihon Universit
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Saeki Katsutoshi
Department Of Electronics And Computer Science College Of Science And Technology Nihon University
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NAKASHIMA Heisuke
Graduate School of Science & Technology, Nihon University
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Nakashima Heisuke
Graduate School Of Science & Technology Nihon University
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SEKINE Yoshifumi
Deparement of Electronics and Computer Science,College of Science and Technology,Nihon University
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SAEKI Katsutoshi
Department of Electronics & Computer Science, College of Science & Technology, Nihon University
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