Pulse-type hardware chaotic neuron model and its bifurcation phenomena
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概要
- 論文の詳細を見る
- 1999-01-01
著者
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Sekine Yoshifumi
Department Of Electronic Engineering College Of Science And Technology Nihon University
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SOMEYA Kazutaka
Department of Electronic Engineering, College of Science and Technology, Nihon University
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SHINOZAKI Hidekazu
Department of Electronic Engineering, College of Science and Technology, Nihon University
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Someya Kazutaka
Department Of Electronic Engineering College Of Science And Technology Nihon University
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Shinozaki Hidekazu
Department Of Electronic Engineering College Of Science And Technology Nihon University
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SEKINE Yoshifumi
Deparement of Electronics and Computer Science,College of Science and Technology,Nihon University
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- CMOS Implementation of a Multiple-Valued Memory Cell Using Λ-Shaped Negative-Resistance Devices(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- CMOS Implementation of Neuron Models for an Artificial Auditory Neural Network
- A Fundamental Consideration for Phase Noise Measurement of Extremely Low Phase Noise Oscillator
- Pulse-type hardware chaotic neuron model and its bifurcation phenomena
- A Minimal Modeling of Neuronal Burst-Firing Based on Bifurcation Analysis