A 1V, 10.4mW Low Power DSP Core for Mobile Wireless Use (Special Issue on Low-power LSIs and Technologies)
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概要
- 論文の詳細を見る
An 1V, 50MHz, 16-bit DSP core was developed using a 0.25-μm Dual Vt library, SRAM, and Mask ROM tailored fro 1V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0V to 1.5V voltage up converter with 59% power efficiency and a 450ps 1V to 2.5V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9V was 8.7mW. which was 40% less than the power of the normal library's at 1.3V, when the PSI-CELP CODEC firmware was run at 40MHz.
- 社団法人電子情報通信学会の論文
- 2000-11-25
著者
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ISHIHARA Teruo
Fujitsu Laboratories Ltd.
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Tsuchiya Atsushi
Fujitsu Labs. Ltd.
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Fukushi Isao
Fujitsu Limited
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Fukushi Isao
Fujitsu Labs. Ltd.
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Shiota Tetsuyoshi
Fujitsu Labs. Ltd.
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Ishihara T
Fujitsu Laboratories Ltd.
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Ishihara Teruo
Fujitsu Laboratories Limited
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KAWASHIMA Shoichiro
Fujitsu Limited
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SASAGAWA Ryuhei
Fujitsu Labs. Ltd.
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SHIBAMOTO Wataru
Fujitsu Labs. Ltd.
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Kawashima S
Fujitsu Labs. Ltd.
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Kawashima Shoichiro
Fujitsu Laboratories Ltd.
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