A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip(Next-Generation Memory for SoC,<Special Section>VLSI Technology toward Frontiers of New Market)

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A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-μm CMOS3-V 1-Mbit device was qualified by a 250℃ bake for a short time retention and 150℃ 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 10^<12> fatigue cycles with an access time of 81ns, 3.0V VDD at 85℃. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.
社団法人電子情報通信学会の論文
2007-10-01