CODEC Hardware Engines for a Low-Power Baseband DSP Macro(Regular Section)

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概要

• 論文の詳細を見る

• The progress made in large-scale integration of the baseband circuits of digital cellular phones now makes it possible to implement a voice CODEC and its related functions in the baseband LSI rather than through a general-purpose digital signal processor. This paper describes an improved hardware solution that enables efficient application of the PSI-CELP CODEC-the most complex CODEC for mobile systems-to the PDC half-rate system through its implementation as a DSP macro in a low-voltage, large-scale LSI. Specific circuit blocks are added as hardware engines to a general-purpose DSP-oriented core. These specific engines were implemented as peripheral circuits for a DSP macro that can be used as a single DSP with an added I/O circuit and is suitable for use in future highly integrated mobile baseband chips. With the assistance of these hardware engines and some additional ALU instructions to achieve efficient programming, the machine speed required for the CODEC can be relatively slow, thus allowing the same architecture to be repeatedly used without needing to set the transistor threshold voltage too low even when the use of deeper sub-micron technologies require a chip to run at a lower supply voltage. We evaluated this DSP-macro architecture using a 0.35 μm CMOS technology test chip. Then we developed a commercial base version using 0.25 μm technology and verified that it can operate at 1.2V and that the PSI-CELP CODEC can be done at 40 MIPS with power consumption of 11 mW. We also verified that the circuit design can be applied up to 0.18 μm technology with a single threshold voltage of 0.3 V. Thus, the design of the DSP macro incorporating the hardware engines provides a great deal of flexibility that should allow its use in chips based on future technologies and the voice CODEC firmware can be effectively re-used. Although the DSP macro architecture was designed mainly through PSI-CELP application analysis, it can process other voice CODECs such as the AMR CODEC for third-generation mobile applications as well as some other mobile baseband functions such as channel CODECs. This approach can also be refined to permit its application to, for example, high-quality audio CODECs.

• 社団法人電子情報通信学会の論文
• 2002-12-01

著者

• GAMBE Hirohisa

  Fujitsu Laboratories Ltd.

• ISHIHARA Teruo

  Fujitsu Laboratories Ltd.

• Ishihara Teruo

  Fujitsu Laboratories Limited

• OTA Yasuji

  Fujitsu Laboratories Limited

• KUMAMOTO Norichika

  Fujitsu Laboratories Limited

• KUNIYASU Yoshio

  Fujitsu Limited

関連論文

• A Low Power Programmable Turbo Decoder Macro Using the SOVA Algorithm(Low-Power System LSI, IP and Related Technologies)
• An Improved Sliding Window Algorithm for Max-Log-MAP Turbo Decoder and Its Programmable LSI Implementation(Electronic Circuits)
• CODEC Hardware Engines for a Low-Power Baseband DSP Macro(Regular Section)
• A 1V, 10.4mW Low Power DSP Core for Mobile Wireless Use (Special Issue on Low-power LSIs and Technologies)

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