An Improved Sliding Window Algorithm for Max-Log-MAP Turbo Decoder and Its Programmable LSI Implementation(Electronic Circuits)
スポンサーリンク
概要
- 論文の詳細を見る
Thanks to the possibility of being able to implement them in decoders in relatively simple ways, turbo codes are being applied to various areas of engineering. Wireless communications is one of the most important applications, where various types of data communications are required and the speed of information and data capacity need to be changed with different rates of parity bit puncturing being adopted to obtain highly efficient transmission. In such applications, adaptation to various turbocoding specifications on a real-time basis is needed as well as good biterror-rate performance. We present a new concept for simplifying metric computation and programmable circuit configurations that focuses on the convolutional decoder, which occupies a significant portion of allocated hardware, and we fundamentally treat a simplified log-domain version of the maximum a posteriori (MAP) algorithm, usually know as the Max-Log-MAP (MLM), as a base algorithm. The sliding window method provides an attractive way of computing metric values for the Max-Log-MAP. However, this algorithm does cause degradation, especially when a high rate code is used, generated by bit puncturing. We propose a new means of avoiding this problem and demonstrate that the sliding window, and a modified version as well as other methods, should be flexibly selected to utilize hardware resources depending on turbo specifications. We demonstrated that our proposed methods provide almost the same BER performance as MLM even when a high rate puncturing rate of 5/6 is applied. Finally, we describe the new hardware architecture that we invented to cope with these programmability issues. We show that a turbo-decoding circuit can be implemented in the processor core and its associated unit to configure an LSI macro circuit. The proposed unit has about 60-K gates. We demonstrate that this architecture can be applied to about the 1.5-Mbps information bit throughput of turbo decoding with a 200-MHz clock cycle, which is achievable with today's advanced CMOS technologies.
- 社団法人電子情報通信学会の論文
- 2005-03-01
著者
-
GAMBE Hirohisa
Fujitsu Laboratories Ltd.
-
OHBUCHI Kazuhisa
Fujitsu Laboratories Ltd.
-
ISHIHARA Teruo
Fujitsu Laboratories Ltd.
-
Ohbuchi Kazuhisa
Yrp R&d Center
-
Ishihara T
Fujitsu Laboratories Ltd.
-
Ishihara Teruo
Fujitsu Laboratories Limited
-
TANAKA Yoshinori
Fujitsu Laboratories Ltd.
-
LI Jifeng
Fujitsu Laboratories Ltd.
関連論文
- A Low Power Programmable Turbo Decoder Macro Using the SOVA Algorithm(Low-Power System LSI, IP and Related Technologies)
- B-5-28 (4,12) Circular16QAMの符号誤り率特性改善の検討(B-5.無線通信システムA(移動通信),一般講演)
- W-CDMA方式の無線系信号方式 (特集 IMT-2000)
- B-5-88 バッファを削減したIR H-ARQにおける再送方法(B-5. 無線通信システムA(移動通信),一般セッション)
- B-5-118 繰り返し数制御によるターボ復号器の回路規模削減効果(B-5.無線通信システムA(移動通信),一般講演)
- B-5-7 ダミービット挿入によるターボ符号の提案(B-5.無線通信システムA(移動通信),通信1)
- Performance Evaluation of Symbol-Wise XOR Based Bi-directional Relaying
- An Improved Sliding Window Algorithm for Max-Log-MAP Turbo Decoder and Its Programmable LSI Implementation(Electronic Circuits)
- CODEC Hardware Engines for a Low-Power Baseband DSP Macro(Regular Section)
- A 1V, 10.4mW Low Power DSP Core for Mobile Wireless Use (Special Issue on Low-power LSIs and Technologies)