A Fully Depleted CMOS/SIMOX LSI Scheme Using a LVTTL-Compatible and Over-2,000-V ESD-Hardness I/O Circuit for Reduction in Active and Static Power Consumption (Special Issue on SOI Devices and Their Process Technologies)

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概要

• 論文の詳細を見る

• In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3V to 2.2V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3V signal can be converted from/to 2.0-1.2V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-μm CMOS/SIMOX, 0.25-μm bulk CMOS and 0.5-μm bulk CMOS, power consumptions are compared. The 0.25-μm CMOS/SIMOX LSI can operate at an internal voltage of 1.2V at the same frequency as the 0.5-μm LSI operating at 3.3V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-μm bulk LVTTL-LSI.

• 社団法人電子情報通信学会の論文
• 1997-03-25

著者

• Ohtomo Y

  Ntt System Electronics Lab. Atsugi‐shi Jpn

• Ohtomo Yusuke

  Ntt System Electronics Laboratories

• Ohtomo Yusuke

  The Authors Are With The Ntt System Electronics Laboratories

• MIZUSAWA Takeshi

  NTT Electronics Technology

• NISHIMURA Kazuyoshi

  NTT System Electronics Laboratories

• SAWADA Hirotoshi

  NTT System Electronics Laboratories

• INO Masayuki

  NTT System Electronics Laboratories

• Ino Masayuki

  Ntt Electronics Corp.

関連論文

• An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
• A Fully Depleted CMOS/SIMOX LSI Scheme Using a LVTTL-Compatible and Over-2,000-V ESD-Hardness I/O Circuit for Reduction in Active and Static Power Consumption (Special Issue on SOI Devices and Their Process Technologies)
• A 40-Gb/s 8×8 ATM Switch LSI Using 0.25-μm CMOS/SIMOX(Special Issue on Multimedia, Network, and DRAM LSIs)
• A High-Performance Multicast Switch and Its Feasibility Study
• A 2.6-Gbps/pin SIMOX-CMOS Low-Voltage-Swing Interface Circuit (Special Issue on Ultra-High-Speed LSIs)
• A 4:1 MUX Circuit Using 1/4 Micron CMOS/SIMOX for High-Speed and Low-Power Applications
• 3-Gb/s CMOS 1:4 MUX and DEMUX ICs
• A Low-Power and High-Speed Impulse-Transmission CMOS Interface Circuit

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