Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
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概要
- 論文の詳細を見る
It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1<__-r<__-n). We show that only (r+n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network.
- 社団法人電子情報通信学会の論文
- 1999-09-25
著者
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Shimizu Kensuke
Faculty Of Engineering Gunma University
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Hirayama Takashi
Department Of Computer And Information Sciences Iwate University
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HIRAYAMA Takashi
Faculty of Pharmaceutical Sciences, Okayama University
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Shimizu K
Gunma Univ. Kiryu‐shi Jpn
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Nishitani Y
Iwate Univ. Morioka‐shi Jpn
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Nishitani Yasuaki
Faculty Of Engineering Gunma University
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KODA Goro
Department of Computer Science, Gunma University
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KODA Goro
Faculty of Engineering, Gunma University
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Hirayama Takashi
Faculty Of Engineering Iwate University
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