Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
スポンサーリンク
概要
- 論文の詳細を見る
In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1 / 2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.
- 2000-03-25
著者
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FUKUI Yutaka
the Faculty of Engineering, Tottori University
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Fukui Y
Faculty Of Engineering Tottori University
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Fukui Y
Graduate School Of Engineering Tottori University
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Ishii Hidekazu
The Faculty Of Engineering Tottori University
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Sumi Yasuaki
Department Of Information Systems Faculty Of Environmental And Information Studies Tottori Universit
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Obote Shigeki
Department Of Media And Telecommunications Engineering Faculty Of Engineering Ibaraki University
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Furuhashi Ryousuke
Kenwood Corporation
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OBOTE Shigeki
the Faculty of Engineering, Tottori University
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SUMI Yasuaki
Tottori SANYO Electric Co., Ltd.
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KITAI Naoki
the Faculty of Engineering, Tottori University
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Kitai Naoki
The Faculty Of Engineering Tottori University
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Fukui Yutaka
The Faculty Of Engineering Tottori University
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