PLL Frequency Synthesizer for Low Power Consumption (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
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概要
- 論文の詳細を見る
In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N+1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.
- 1997-03-25
著者
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FUKUI Yutaka
Faculty of Engineering, Tottori University
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Fukui Y
Faculty Of Engineering Tottori University
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Fukui Y
Graduate School Of Engineering Tottori University
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Fukui Yutaka
Faculty Of Engineering Setsunan University
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Sumi Yasuaki
Department Of Information Systems Faculty Of Environmental And Information Studies Tottori Universit
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Obote Shigeki
Department Of Media And Telecommunications Engineering Faculty Of Engineering Ibaraki University
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Obote Shigeki
Faculty Of Engineering Ibaraki University
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SUMI Yasuaki
Tottori SANYO Electric Co., Ltd.
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SYOUBU Kouichi
Nippon Hoso Kyokai
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SYOUBU Kouichi
Faculty of Engineering, Tottori University
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TSUDA Kazutoshi
Faculty of Engineering, Tottori University
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Tsuda Kazutoshi
Japan Radio Co.
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