Top-Down Co-simulation of Hardware/Software Co-designs for Embedded Systems Based Upon a Component Logical Bus Architecture (Special Section on VLSI Design and CAD Algorithms)

概要

論文の詳細を見る
We propose a top-down approach for co-simulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.
社団法人電子情報通信学会の論文
1997-10-25