不整合転位密度の制御によるGaAs/Siの応力低減(<特集>ヘテロエピタキシー機構)

概要

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The growth process for stress reduction in GaAs epilayers grown on Si (100) by molecular beam epitaxy was studied. The GaAs buffer layers were grown at 250℃ on misoriented Si(100) substrates (0〜6°off) with various thickness (0.05〜0.20μm), and then annealed at various temperatures (300〜600℃). The GaAs overlayers were sequentially grown at 300℃. In this process, the misfit dislocation density in the GaAs epilayer was controlled in the buffer layer formation process by changing the buffer layer thickness, the buffer layer annealing temperature and the off-angle of Si substrate, and the density was quenched during overlayer growth. The minimum-stressed GaAs epilayer was grown on 3°-off substrate with a 0.1 μm-thick buffer layer annealed at 500℃. In addition, the asymmetric stresses were observed between [011] and [01^^-1]. This asymmetry is caused by the difference in dislocation velocities or dislocation nucleation energies between α- and β-dislocations. The crystalline quality of GaAs epilayer should be improved in the low-stressed conditions.
日本結晶成長学会の論文
1993-12-25